With rapid growing of transistors amount in an integrated circuit (IC), areas of chip being used is increased accordingly, resulting problems such as delay time and power consumption of signal to get worse each day. In order to improve such critical problem in delay time and power consumption, a three dimensional IC (3DIC) stacking technology is an effective solution under development today. The technology performs vertically stacking to a plurality of chips in 3D space, signals and power voltages are transmitted by utilizing through silicon vias (TSVs) being passed through the silicon substrate in between different chips, so as to achieve an optimal effect in size reduction.
Processing technology of the 3DIC mainly focused in three steps: first step includes forming TSV channels and filling a conductive metal; second step includes performing a thinner process to wafers; and third step includes stacking and bonding chips together. In the first step, as restricted by the processing technology at the present stage, an insulating thin film (e.g., SiO2) on sidewalls of TSVs may be broken or invaded by foreign impurity, resulting an open-circuit of the TSVs or a short-circuit of the silicon substrate. Also, in the third step when a plurality of ICs are stacked, due to small position offset, the TSVs may not be correctly turned on to each other, resulting an open-circuit, that is, TSVs may fail to provide effective paths between different chips for transmitting signal.
In conventional 2DIC design, the problem in data transmission may be prevented by utilizing a plurality of paths to transmit the same signal at the same time. However, in 3DIC technology, once one of the TSVs has short-circuit on the silicon substrate, leakage current generated by power voltage may flow into the silicon substrate through the TSV, resulting overall voltage level in the silicon substrate to shift and become unstable, such that errors in transmission may occur since signals transmitted in other TSVs may also be affected by shifted voltage level in the silicon substrate. Therefore, many of manufacturers in 3DIC field are in searching for a bidirectional data transmission circuit with capabilities of automatically detecting short defect of the TSVs and self-repairing data.
In addition, in 3DIC field, other than utilizing the TSVs to perform signal transmission within the chips, it is also required for the 3DIC to transmit signals to circuits outside of the chips through bonding pads. FIG. 1 is a schematic view illustrating a chip inner circuit 10, a bonding pad 20, an output buffer driving circuit 30 and an external circuit 40. In which, an output signal may be transmitted by the output buffer driving circuit 30 to the external circuit 40, or an input signal of the external circuit 40 may be transmitted to the chip inner circuit 10 through the bonding pad 20. As shown in FIG. 1, generally, when a signal transmission is performed by the chip inner circuit 10, the output signal from an output terminal Nout may be clamped by two electrostatic protection diodes D1 and D2 with a power voltage VDD and a ground voltage GND, and the output terminal Nout may be connected to the output buffer circuit 30 for buffering the output signal. The output signal of the chip inner circuit 10 may be transmitted to the external circuit 40 through a resistor R1 and the bonding pad 20, in such case a capacitive loading mounted when transmitting signals from the chip inner circuit 10 to the external circuit 40 is, for example, generally ranged from 20 pf to 40 pf. Therefore, besides the capabilities of automatically detecting short defect of the TSV and self-repairing the data, the bidirectional data transmission circuit is also expected to have sufficient load driving capability to drive the signals to the external circuit.